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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM32A732/D
Advance Information
128KB/256KB Secondary Cache Module
With Tag, Valid, and Dirty for i486 Processor Systems
This family of cache modules is well suited to provide the secondary cache for the Intel 82420 PCI chipset. This family provides the 128K Byte and 256K Byte cache sizes with valid, dirty and a choice of 7, 8, or 9 tag bits. The tag/valid bits have 12 ns access times for zero wait states at 33 MHz clock speeds. The PD pins map into the configuration register of the 82420 for auto-configuration of the cache controller during system startup. * Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48 * Single 5 V 10% Power Supply * All Inputs and Outputs are TTL Compatible * Three State Outputs * Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz * Cache Byte Write, Bank Chip Enable, Bank Output Enable * Decoupling Capacitors are Used for Each Fast Static RAM * High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes
MCM32A732 MCM32A832 MCM32A932 MCM32A764 MCM32A864 MCM32A964
112-LEAD CARD EDGE CASE 1112-01 TOP VIEW 1
45 46
56
BurstRAM is a registered trademark of Motorola. I486 is a registered trademark Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1 6/95
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM32A732/764*MCM32A832/864*MCM32A932/964 1
PIN ASSIGNMENT CACHE MODULE 112-LEAD CARDEDGE TOP VIEW
VSS DQ0 DQ2 DQ4 DQ6 VCC NC DQ8 DQ10 DQ12 VSS DQ14 DQ16 DQ18 DQ20 VCC DQ22 NC DQ24 DQ26 VSS DQ28 DQ30 LA2 LA3 VCC A4 A6 A8 A10 A12 A14 A16 NC VSS DIRTYD TDQ0 TDQ2 TDQ4 VSS TDQ6 VALID TE TWE VCC VSS TG DIRTYWE DIRTYE VCC G0 E0 PD0 PD2 PD4 VSS 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 VSS DQ1 DQ3 DQ5 DQ7 VCC NC DQ9 DQ11 DQ13 VSS DQ15 DQ17 DQ19 DQ21 VCC DQ23 NC DQ25 DQ27 VSS DQ29 DQ31 HA2 HA3 VCC A5 A7 A9 A11 A13 A15 NC NC VSS DIRTYQ TDQ1 TDQ3 TDQ5 VSS TDQ7* TDQ8** ALE WE0 VCC VSS WE1 WE2 WE3 VCC G1 E1 PD1 PD3 NC VSS
PD4 NC VCC VCC VCC VCC VCC VCC
PD3 NC VCC NC NC VCC NC NC
PD2 NC NC NC VCC NC NC VCC
PD1 NC NC NC NC VCC VCC VCC
PD0 NC VCC VCC VCC NC NC NC
Cache Size -- 128KB 128KB 128KB 256KB 256KB 256KB
Main Memory Max -- 16MB 32MB 64MB 32MB 64MB 128MB
Module No Module 32A732 32A832 32A932 32A764 32A864 32A964
PIN NAMES
A4 - A19 . . . . . . . . . . . . . . . . . . . . . . Address Inputs HCA2, HCA3 . . . . . . . Upper Bank Address Inputs LCA2, LCA3 . . . . . . . . Lower Bank Address Inputs ALE . . . . . . . . . . . . . . . . . . . . Address Latch Enable Wx . . . . . . . . . . . . . . . . . . . . . . . . Byte Write Enable E0, E1 . . . . . . . . . . . . . . . . . . . . . Bank Chip Enable G0, G1 . . . . . . . . . . . . . . . . . . . Bank Output Enable DQ0 - DQ31 . . . . . . . . . . Cache Data Input/Output TDQ0 - TDQ8 . . . . . . . . . . . Tag Data Input/Output TWE . . . . . . . . . . . . . . . . . . . . . . . . Tag Write Enable TG . . . . . . . . . . . . . . . . . . . . . . . . Tag Output Enable TE . . . . . . . . . . . . . . . . . . . . . . . . . . Tag Chip Enable VALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid Bit DIRTYWE . . . . . . . . . . . . . . . . . . Dirty Write Enable DIRTYE . . . . . . . . . . . . . . . . . . . . . Dirty Chip Enable DIRTYD . . . . . . . . . . . . . . . . . . . . . . Dirty Data Input DIRTYQ . . . . . . . . . . . . . . . . . . . . . Dirty Data Output PD0 - PD4 . . . . . . . . . . . . . . . . . . Presence Detect NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connect VCC . . . . . . . . . . . . . . . . . . . . . . +5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
* No Connect for 32A864, 32A832 ** No Connect for 32A764, 32A864, 32A732, 32A832
MCM32A732/764*MCM32A832/864*MCM32A932/964 2
MOTOROLA FAST SRAM
486 256KB CACHE MODULE BLOCK DIAGRAM WITH 9 TAG BITS
32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G
W0
E
E
W1
E
E
W2
E
E
W3
E E0 G0 LCA3 LCA2 DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 DIRTYQ DIRTYD DIRTYWE ALE A4 - A17 TDQ0 - TDQ8 VALID TWE 14 8 8 8 8
E E1 G1 HCA3 HCA2
A0 - A13 16K x 1 Dout Din W 74F373 A0 - A13 DQ0 - DQ8 DQ9 16K x 10 W
DIRTYE
TE TG
MOTOROLA FAST SRAM
MCM32A732/764*MCM32A832/864*MCM32A932/964 3
486 128KB CACHE MODULE BLOCK DIAGRAM WITH 9 TAG BITS
32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G 32K x 8 A2 - A14 DQ0 - DQ7 W A0 A1 G
W0
E
W1
E
W2
E
W3 NC NC NC NC E1 G1 HCA3 HCA2
E E0 G0 LCA3 LCA2 DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 DIRTYQ DIRTYD DIRTYWE ALE A4 - A17 TDQ0 - TDQ8 VALID TWE
A0 - A12 8K x 1 Dout Din W 74F373 A0 - A12 DQ0 - DQ8 DQ9 8K x 10 W
DIRTYE
TE TG
MCM32A732/764*MCM32A832/864*MCM32A932/964 4
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don't Care)
E H L L L G X H L X W X H H L Mode Not Selected Output Disabled Read Write VCC Current ISB1, ISB2 ICCA ICCA ICCA Output High-Z High-Z Dout High-Z Cycle - - Read Cycle Write Cycle
NOTE: E = Exx, ET; W = Wxx, WT, WA; G = GA, GB
ABSOLUTE MAXIMUM RATINGS
Rating Power Supply Voltage Voltage Relative to VSS For Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 11.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5* Typ 5.0 -- -- Max 5.5 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns)
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Output High Voltage (IOH = - 4.0 mA) Output Low Voltage (IOL = 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min -- -- 2.4 -- Max 10 10 -- 0.4 Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax) AC Standby Current (E = VIH, VCC = Max, f = fmax) CMOS Standby Current (VCC = Max, f = 0 MHz, E VCC - 0.2 V Vin VSS + 0.2 V, or VCC - 0.2 V) Symbol ICCA ISB1 ISB2 32Ax32 33 MHz 750 180 120 32Ax64 33 MHz 1250 300 200 Unit mA mA mA
MOTOROLA FAST SRAM
MCM32A732/764*MCM32A832/864*MCM32A932/964 5
CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25C, Periodically sampled rather than 100% tested)
Characteristic Cache Address Input Capacitance Control Pin Input Capacitance I/O Capacitance Tag Address Input Capacitance (E, W) Symbol Cin Cin CI/O Cin Max 48 8 8 18 Unit pF pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
READ CYCLE (See Notes 1 and 2)
Data Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z xCA2-3 (Transparent Mode) A4 - A19 Symbol tAVAV tAVQV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ Min 30 -- -- -- -- 4 4 -- 0 -- Max -- 20 25 20 10 -- -- 9 -- 8 Tag/Valid Min 30 -- -- -- -- 4 4 -- 0 -- Max -- 12 12 12 6 -- -- 7 -- 6 Dirty Min 30 -- -- -- -- 4 4 -- 0 -- Max -- -- 25 20 -- -- -- 9 -- -- Unit ns ns ns ns ns ns ns ns ns 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 Notes 3 9 4
NOTES: 1. W is high for read cycle. 2. E = Exx, ET; W = Wxx, WT, WA; G = GA, GB 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E = VIL, G = VIL). 9. TAG Address Access Time tAVTV.
AC TEST LOADS
+5 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MCM32A732/764*MCM32A832/864*MCM32A932/964 6
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (CACHE DATA OUT) PREVIOUS DATA VALID tAVQV Q (TAG DATA OUT) PREVIOUS DATA VALID tAVTV DATA VALID DATA VALID
READ CYCLE 2 (See Note 3)
tAVAV A (ADDRESS) tAVQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (TAG DATA OUT) HIGH-Z DATA VALID HIGH-Z tGHQZ tELQV tEHQZ
VCC SUPPLY CURRENT ISB
ICC
tELICCH
tEHICCL
MOTOROLA FAST SRAM
MCM32A732/764*MCM32A832/864*MCM32A932/964 7
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
Data Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Setup to Write Time Data Hold from Write Time Write Low to Output High-Z Write High to Output Active Write Recovery Time (A4 - A5) (A6 - A19) Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 30 2 10 20 12 8 0 0 4 0 Max -- -- -- -- -- -- -- 8 -- -- Tag/Valid Min 30 -- 2 10 12 6 0 0 4 0 Max -- -- -- -- -- -- -- 6 -- -- Dirty Min 30 -- 10 20 12 8 0 0 4 0 Max -- -- -- -- -- -- -- 8 -- -- Unit ns ns ns ns ns ns ns ns ns 6,7,8 6,7,8 Notes 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. E = Exx, ET; W = Wxx, WT, WA; G = GA, GB 3. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. If G VIH, the output will remain in a high impedance state. 6. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 7. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 8. This parameter is sampled and not 100% tested.
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX
MCM32A732/764*MCM32A832/864*MCM32A932/964 8
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
Data Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Setup to Write Time Data Hold from Write Time Write Recovery Time (A4 - A5) (A6 - A19) Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 30 2 10 20 15 8 0 0 Max -- -- -- -- -- -- -- -- Tag/Valid Min 30 -- 2 10 10 6 0 0 Max -- -- -- -- -- -- -- -- Dirty Min 30 -- 10 20 15 8 0 0 Max -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns Notes 4
NOTES: 1. A write occurs during the overlap of E low and W low. 2. E = Exx, ET; W = Wxx, WT, WA; G = GA, GB 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
WRITE CYCLE 2 (E Controlled, See Note 1)
tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tAVEL tELEH tELWH tEHAX
W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX
Q (DATA OUT)
HIGH-Z
MOTOROLA FAST SRAM
MCM32A732/764*MCM32A832/864*MCM32A932/964 9
ORDERING INFORMATION
(Order by Full Part Number) 32Ax32 32Ax64
MCM
Motorola Memory Prefix Part Number (x = Tag Bits)
XX
XX
Speed (33 = 33 MHz) Package (SG = Gold Pad SIMM)
Full Part Numbers -- MCM32A732SG33 MCM32A764SG33 MCM32A832SG33 MCM32A864SG33 MCM32A932SG33 MCM32A964SG33
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM32A732/764*MCM32A832/864*MCM32A932/964 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
112-LEAD CARD EDGE MODULE CASE 1112-01 A C
NOTE 4
COMPONENT AREA
B
-Y- VIEW AA
102
101
112
COMPONENT AREA
BACK VIEW
57
MOTOROLA FAST SRAM
EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E
FULL
R
56
46
45
1
V
NOTE 4
AB
NOTE 5
2X
F L
AC -X-
M E
J -T- SIDE VIEW
NOTE 6
0.012 (0.3)
M
EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E EEEEEEEEEE EE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEE E E
112X
FRONT VIEW
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS C AND V DEFINE A DOUBLE-SIDED MODULE. 5. DIMENSION AB DEFINES OPTIONAL SINGLE-SIDED MODULE. 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. DIM A B C D E F G H J K L M N R V W AB AC INCHES MIN MAX 3.130 3.150 1.190 1.210 --- 0.365 0.033 0.037 2.415 2.425 0.075 BSC 0.050 BSC --- 0.030 0.055 0.069 0.210 --- 0.605 0.615 2.305 2.315 0.110 REF 0.285 0.305 0.285 --- 0.040 0.060 --- 0.220 0.072 0.076 MILLIMETERS MIN MAX 79.50 80.01 30.23 30.73 --- 9.27 0.84 0.94 61.34 61.60 1.91 BSC 1.27 BSC --- 0.76 1.40 1.75 5.33 --- 15.37 15.62 58.55 58.80 2.79 REF 7.24 7.75 7.24 --- 1.02 1.52 --- 5.59 1.83 1.93
D
L
R
RW
(N)
VIEW AA
EEE EE E EEE EE E EEE EE E EEE EE E
0.004 (0.10)
TYX
S
112X
K
112X
H
108X
G
MCM32A732/764*MCM32A832/864*MCM32A932/964 11
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM32A732/764*MCM32A832/864*MCM32A932/964 12
*MCM32A732/D*
MCM32A732/D MOTOROLA FAST SRAM

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